1. Field of the Invention
The present invention relates to an insert block for loading semiconductor devices under test and, more particularly, to an insert block for testing semiconductor devices that transports, fixes, and centers them under test.
2. Description of the Related Art
After wafer processing, semiconductor chips cut from the wafer are assembled into semiconductor packages. Test processes are carried out to verify not only the electric characteristics but also the reliability, including functionality, of the semiconductor packages. An apparatus, usually a handler, is used to test fabricated semiconductor packages and sort tested packages.
A handler for testing semiconductor packages can generally be classified as a vertical handler and a horizontal handler. The vertical handler receives semiconductor packages sequentially, tests them, and sorts them according to their test results. The horizontal handler uses multiple trays, and each tray is loaded with multiple semiconductor packages. Tests are performed when the trays are loaded with semiconductor packages. Being moved from the tested tray to a new tray, tested packages are sorted into bins according to their test results.
The horizontal handler includes a loading area, supply area, test area, and sorting area. In the loading area, insert blocks of an insert tray are loaded with multiple untested semiconductor packages by picking them from a receiving tray loaded with untested packages prior to testing. In the supply area, insert trays loaded with untested packages are transported to the test area. In the test area, testing on the semiconductor packages contained in the insert blocks of the insert tray is performed. In the sorting area, tested semiconductor packages from the insert trays are sorted according to their test results and the sorted packages are loaded into a new receiving tray. After sorting, the insert trays are transported back to the loading area, and these semiconductor package test processes are repeated.
In other words, in semiconductor package test processes using horizontal handlers, multiple insert blocks are arranged horizontally in an insert tray, and each insert block is loaded with multiple semiconductor packages under test.
FIG. 1 is a schematic perspective view showing an insert tray of a conventional horizontal handler.
Referring to FIG. 1, multiple insert blocks 30 are arranged at a designated interval in a tray frame 20 of the insert tray 100. Insert blocks 30 are coupled with the tray frame 20 via coupling pins 101. The coupling pin 101 is inserted into a coupling hole 102 on the tray frame 20 and fixed. Devices under test (DUT) such as semiconductor packages are loaded in each insert block 30.
FIG. 2 is a sectional view showing the conventional insert block, taken along the x–z plane in FIG. 1, for testing semiconductor packages.
The same insert block for testing semiconductor packages as the one shown in FIG. 2 is already made public in 2002 via Korean Patent Publication No. 2002-61879 filed by Samsung Electronics Corporation.
As shown in FIG. 2, the insert block 30 includes a block body 31, a latch 32, and a latch cap 33.
The block body 31 includes a fixing hole 31 a to fix the insert block 30 during testing, a loading space G1 to accommodate a semiconductor device under test (DUT, hereinafter), and a loading member 31b where the DUT is loaded.
Various types of DUTs can be loaded, and a BGA (ball grid array) package is shown here. A plurality of solder balls B1, which act as external terminals of the DUT, are provided on the bottom surface of the DUT, and these contact with corresponding contact pins C1 of a test socket (not shown).
FIG. 3 is a view showing in detail the P portion of FIG. 2. Hereinafter, the latch 32 and latch cap 33 are explained in detail with reference to FIG. 3.
The latch 32 turns in the M1 or M2 direction with its rotating shaft 32a as the axis of rotation. Turning in the M1 direction, the latch 32 applies force to the side and top surface of the DUT. A sliding groove 32b is formed in the latch 32, and a hanging bar 33a of the latch cap 33 is inserted therein.
The latch cap 33 moves up and down in the direction of the z-axis along a cap guide (31c in FIG. 2). The latch cap 33 includes the cylindrical-shaped hanging bar 33a, which is inserted into the sliding groove 32b of the latch 32. Consequently, the up and down movement of the latch cap 33 causes the latch 32 to rotate in the M1 or M2 direction via the cam-like behavior of the hanging bar 33a and sliding groove 32b. 
As shown in FIG. 3, since the latch 32 applies pressure to the top surface of the DUT downward along the z-axis and to the side thereof toward the right along the x-axis, the DUT comes to be fixed relative to the z-axis and be aligned along the x-axis with respect to the contact pins of the test socket.
FIG. 4 is a cross-sectional view, taken along the y-z plane, showing the DUT loaded in the conventional insert block contacts with the contact pins of the test socket. However, as shown in FIG. 1, the latch 32 of the conventional insert block 30 for testing semiconductor devices aligns the DUT only with respect to the x-axis, and the DUT may float considerably along the y-axis. Given that the tolerances with respect to the x and y-axes of the DUT are in the range of about 0.1 to about 0.2 mm, there is a problem that, seen from the x-y plane, the DUT may not be centered relative to the contact pins of the test socket. Namely, as shown in FIG. 4, poor contact between the solder balls B1 and the contact pins C1 can be caused by the bad alignment therebetween with respect to the y-axis. Furthermore, the contact pins C1 exert pressure upward along the z-axis on the side N1 apart from the center of the solder balls B1, and this eccentric pressure can result in a critical problem by detaching the solder balls B1 from the DUT.
Accordingly, there is a need for an enhanced insert block for testing semiconductor devices which is capable of centering firmly semiconductor devices under test with respect to the contact pins of the test socket along the two perpendicular axes of the top or bottom surface of the semiconductor device.